In nonvolatile memories, such as flash memory, it is desirable to shrink the size of a conventional memory cell. A conventional memory cell typically includes a gate stack, a source, a drain, and a channel disposed between the source and drain. The gate stack typically includes at least a floating gate and a control gate. Shrinking the size of conventional memory cells allows a higher density of memory cells to be provided in a given area of the semiconductor. However, shrinking the size of the conventional memory cell can adversely affect the performance of the conventional memory cell.
For example, as the size of the conventional memory cell decreases, the length of the channel decreases. This decrease in the length of the channel results in short channel effects which adversely affect the performance of the memory cell. One short channel effect is called drain induced barrier lowering ("DIBL"). DIBL can cause variations in the threshold voltage with drain voltage. As the threshold voltage lowers, the memory cell can be erroneously turned on, decreasing the reliability of the memory cell.
A conventional method for reducing such short channel effects proposes increasing the channel dopant. Increasing the channel dopant increases the threshold voltage at shorter channels. However, an increase in the dopant near the source of the device can cause the electric field between the source and the underlying semiconductor to increase. This increased electric field can adversely affect the performance of the memory cell, particularly during erase.
During a conventional erase, a high negative bias is applied to the gate stack and a high positive bias is applied to the source. This allows charge carriers to tunnel between the floating gate and the source. Because of the concentration of channel dopant near the source, a high electric field is also generated between the substrate and the source. This high electric field causes band-to-band tunneling, causing a substrate current to flow between the substrate and the source. This substrate current can be much larger than the expected erase current. As a result, a voltage drop across the memory cell is generated. Because the sources of many memory cells are coupled to the same line, the bias applied to each memory cell can drop significantly along the line. As a result, a memory cell near the end of the line will be subjected to a lower voltage. Consequently, memory cells along the line are erased at different rates. Different erase rates along a single line are undesirable.
One conventional method that has been proposed for reducing the substrate current and increasing the threshold voltage is to use a non-uniform channel profile. The nonuniform channel profile would have a higher concentration of channel dopant near the drain than near the source. However, processing of such a memory cell would be more difficult because of the introduction of an additional mask to prevent channel dopant from reaching the area of the semiconductor near the source. In addition, such an implant typically uses a high angle implant. A high angle implant is used to place the channel dopant in front of the portion of the drain closest to the gate stack. The channel dopant is provided in this area because the implant in the drain, typically arsenic, may prevent the channel dopant from diffusing into the channel. Manufacturers typically implant at an angle of approximately seven degrees or less. Thus, in addition to requiring an extra mask, this conventional method cannot easily performed by manufacturers because of the high angle implant.
Accordingly, what is needed is a system and method for reducing short channel effects without significantly complicating processing. The present invention addresses such a need.